This invention relates to a semiconductor integrated circuit that has a CPU and an embedded programmable device, and in particular, it relates to measures for improvement in processing ability.
Programmable devices referred to as PLD (Programmable Logic Device) or FPGA (Field Programmable Gate Array) are widely known (hereinafter referred to as FPGA in this specification). FPGA is a device that enables the user to program its circuit configuration, and has a merit in which the circuit designed by the user is composed immediately to realize the operation. Especially in case of FPGA where circuit configuration is repeatedly recomposed, it also has a merit of improving the processing ability by flexibly changing the necessary circuit configuration on each occasion.
Furthermore, in recent years, it has been proposed to embed the FPGA and CPU into a single semiconductor integrated circuit. In such a semiconductor integrated circuit, in addition to the changes in the program of the conventional CPU, since it has become possible to change the circuit configuration of FPGA, it becomes possible to respond more flexibly to changes of the system.
As an example of conventional semiconductor integrated circuits that has a CPU and an embedded FPGA, there is the one disclosed in Japanese Patent Laid-Open Publication No. Hei. 5-242050. The disclosed circuit has a CPU and an embedded FPGA, and a method in which a part of the operation to be processed is executed by the circuit composed in the FPGA is also disclosed.
However; in the above-mentioned conventional semiconductor integrated circuit that has a CPU and an embedded FPGA, there is a problem in which, in a case where instruction to be processed by FPGA is provided, if a circuit for executing such a processing is not composed in the FPGA, it is handled as undefined operation and the process is suspended.
In addition, in the above-mentioned conventional semiconductor integrated circuit that has a CPU and an embedded FPGA, in a case where the circuit composed in the FPGA is fixed, it does not take advantage of the FPGA characteristics in which the circuit configuration is changed dynamically and it cannot respond flexibly to the necessary circuits on each occasion. Thus, there were limits to the processing ability improvement.
Furthermore, if the circuits composed in the FPGA are changed dynamically, it is necessary for users to designate the timing of circuit configuration change beforehand, and changes in circuit configuration cannot be executed automatically. Moreover, when different users execute different processing on the same semiconductor integrated circuit, it is necessary to designate circuit configuration of the FPGA and the timing of circuit configuration change.
In other words, in a case of conventional semiconductor integrated circuits that has a CPU and an embedded FPGA, there is a problem in which processing ability improvement based on FPGA is not able to be executed automatically.